HPCA-11 Call for Papers

General Chair
Justin Rattner, Intel

Program Chair
Josep Torrellas, Univ. of Illinois

Program Committee
Sarita Adve, Univ. of Illinois
David Albonesi, Cornell Univ.
Krste Asanovic, MIT
Ricardo Bianchini, Rutgers Univ.
Angelos Bilas, Univ. of Crete
Pradip Bose, IBM
Brad Calder, Univ. of California, San Diego
John Carter, Univ. of Utah
Alok Choudhary, Northwestern Univ.
Tom Conte, North Carolina State Univ.
Jose Duato, Univ. Politecnica Valencia
Michel Dubois, Univ. of Southern California
Kemal Ebcioglu, IBM
Kourosh Gharachorloo, Google
Antonio Gonzalez, Univ. Politecnica Catalunya
Rajiv Gupta, Univ. of Arizona
Michael Huang, Univ. of Rochester
Mary Jane Irwin, Pennsylvania State Univ.
Lizy John, Univ. of Texas
David Kaeli, Northeastern Univ.
Steve Keckler, Univ. of Texas
Diana Marculescu, Carnegie Mellon Univ.
Shubu Mukherjee, Intel
Mark Oskin, Univ. of Washington
Timothy Pinkston, Univ. of Southern California
Steve Scott, Cray
Andre Seznec, IRISA/INRIA
John Shen, Intel
Anand Sivasubramaniam, Penn. State Univ.
Kevin Skadron, Univ. of Virginia
Yan Solihin, North Carolina State Univ.
James Smith, Univ. of Wisconsin
Mateo Valero, Univ. Politecnica Catalunya
T. N. Vijaykumar, Purdue Univ.
Yuanyuan Zhou, Univ. of Illinois

Industry Liaison Chairs
Konrad Lai, Intel
Sanjay Patel, Univ. of Illinois
Local Arrangements Chair
Murali Annavaram, Intel
Workshop and Tutorial Chair
Jared Stark, Intel
Publicity and Publications Chair
Christos Kozyrakis, Stanford Univ.
Finance and Registration Chair
Pradeep Dubey, Intel
Web Chair
Wei Liu, Univ. of Illinois

The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture. Topics of interest include, but are not limited to:

• Processor architectures
• Cache and memory systems
• Parallel computer architectures
• Impact of technology on architecture
• Power-efficient architectures and techniques
• High-availability architectures
• High-performance I/O systems
• Embedded and reconfigurable architectures
• Interconnect and network interface architectures
• Network processor architectures
• Innovative hardware/software trade-offs
• Impact of compilers on architecture
• Performance evaluation of real machines

Authors should submit an abstract before Monday, July 12, 2004, 9pm PST. They should submit the full version of the paper before Monday, July 19, 2004, 9pm PST. No extensions will be granted. The full version should be a PDF file that does not exceed 6,000 words according to the instructions in http://www.hpcaconf.org/hpca11   Papers that exceed the length limit or that cannot be viewed using Adobe Acrobat Reader (version 3.0 or higher) may not be reviewed. Papers should be submitted for blind review. Please indicate whether the paper is a student paper for best student paper nominations.

Papers will be evaluated based on their novelty, fundamental insights, and potential for long-term contribution. New-idea papers are encouraged.

Submission issues should be directed to the program chair at torrellas@cs.uiuc.edu. Workshop and tutorial submissions should be directed to the workshop and tutorial chair at jared.w.stark@intel.com.

Important dates

• Abstract submission: July 12, 2004, 9pm PST (firm deadline)
• Paper submission: July 19, 2004, 9pm PST (firm deadline)
• Workshop and tutorial proposals due: August 13, 2004
• Notification of paper outcome: September 25, 2004