HPCA-11 Final Program



Saturday February 12, 2005


8:30-5:00
All Day Events
Tutorial T2: All You Want To Know About Circuits As An Architect But Were Afraid To Ask
Shih-Lien Lu, MRL/MTL Intel
Steven Hsu, CRL/MTL Intel
Workshop W1: CAECW-8: Computer Architecture Evaluation using Commercial Workloads
Kimberly Keeton, HP Labs
Lieven Eeckhout, Ghent University
Pankaj Mehra, HP
Ravi Iyer, Intel Labs
Russell Clapp, Fabric7 Systems, Inc.
Workshop W2: HPCRI: High Performance Computing Reliability Issues
Padma Apparao, Intel Labs
Greg Averill, Intel Labs
1:00-5:00
Afternoon Events
Tutorial T1: A Practical Approach To Performance Analysis And Modeling Of Large-Scale Systems
Adolfy Hoisie, Los Alamos National Laboratory
Darren Kerbyson, Los Alamos National Laboratory


Sunday February 13, 2005


8:30-12:00
Morning Events
Tutorial T3: Volatile Memory Performance Comparison
J. Thomas Pawlowski, Micron Technology, Inc.
8:30-5:00
All Day Events
Workshop W4: INTERACT-9: Interaction between Compilers and Computer Architectures
Gyungho Lee, University of Illinois at Chicago
Wei-Chung Hsu, University of Minnesota
Workshop W5: PPHEC-2: Productivity and Performance in High-End Computing
Ram Rajamony, IBM
Workshop W6: Hardware Performance Monitor Design and Functionality
Olaf Lubeck, Los Alamos National Laboratory
Phil Mucci, University of Tennessee
Mike Lang, Los Alamos National Laboratory
Rob Fowler, Rice University
1:00-5:00
Afternoon Events
Workshop W3: Architecture Research using FPGA Platforms
Arvind, MIT
Krste Asanovic, MIT
Derek Chiou, UT Austin
James Hoe, CMU
Christoforos Kozyrakis, Stanford
Shih-Lien Lu, MRL/MTL Intel
6:30-8:00 Reception at the hotel


Monday February 14, 2005


8:15-8:30 Welcome
8:30-9:30 Keynote Speech: Trends in High-Performance Processors
Fred Weber, Chief Technology Officer, AMD

Chair: Josep Torrellas
9:30-10:00Break
10:00-12:00 SESSION 1: PROCESSOR ARCHITECTURE
Chair: Antonio Gonzalez, Universitat Politecnica de Catalunya and Intel Labs

Multithreaded Value Prediction [PDF]
Nathan Tuck, University of California, San Diego
Dean M. Tullsen, University of California, San Diego
Checkpointed Early Load Retirement [PDF]
Nevin Kιrman, Cornell University
Meyrem Kιrman, Cornell University
Mainak Chaudhuri, Cornell University
José F. Martínez, Cornell University
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures [PDF] [Slides]
Rajeev Balasubramonian, University of Utah
Naveen Muralimanohar, University of Utah
Karthik Ramani, University of Utah
Venkatanand Venkatachalapathy, University of Utah
A Small, Fast and Low-Power Register File by Bit-Partitioning [PDF] [Slides]
Masaaki Kondo, University of Tokyo
Hiroshi Nakamura, University of Tokyo
12:00-1:30Intel-sponsored lunch
1:30-3:30 SESSION 2: TEMPERATURE, ENERGY, AND POWER
Chair: Krste Asanovic, MIT

Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses [PDF]
Krishnan Sundaresan, Michigan State University
Nihar R. Mahapatra, Michigan State University
Distributing the Frontend for Temperature Reduction [PDF]
Pedro Chaparro Monferrer, Universitat Politecnica de Catalunya and Intel Labs
Grigorios Magklis, Universitat Politecnica de Catalunya and Intel Labs
José González, Universitat Politecnica de Catalunya and Intel Labs
Antonio González, Universitat Politecnica de Catalunya and Intel Labs
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures [PDF] [Slides]
Yingmin Li, University of Virginia
David Brooks, Harvard University
Zhigang Hu, IBM T.J.Watson Research Center
Kevin Skadron, University of Virginia
Tapping ZettaRAM for Low-Power Memory Systems [PDF] [Slides]
Ravi K. Venkatesan, North Carolina State University
Ahmed S. AL-Zawawi, North Carolina State University
Eric Rotenberg, North Carolina State University
3:30-4:00Break
4:00-6:00 SESSION 3: COMMUNICATION ARCHITECTURES
Chair: Timothy Pinkston, University of Southern California

An Efficient Programmable 10 Gigabit Ethernet Network Interface Card [PDF] [Slides]
Paul Willmann, Rice University
Hyong-youb Kim, Rice University
Scott Rixner, Rice University
Vijay S. Pai, Purdue University
A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks [PDF] [Slides]
J. Duato, Universitat Politecnica de Valencia, Spain
I. Johnson, Xyratex, United Kingdom
J. Flich, Universitat Politecnica de Valencia, Spain
F. Naven, Xyratex, United Kingdom
P. García, Universidad de Castilla-La Mancha, Spain
T. Nachiondo, Universitat Politecnica de Valencia, Spain
Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems [PDF]
Xuning Chen, Princeton University
Yue-kai Huang, Princeton University
Li-Shiuan Peh, Princeton University
Paul Prucnal, Princeton University
Gu-Yeon Wei, Harvard University
Scatter-Add in Data Parallel Architectures [PDF]
Jung Ho Ahn, Stanford University
Mattan Erez, Stanford University
Bill Dally, Stanford University
6:30-8:00TCCA Business Meeting


Tuesday February 15, 2004


8:00-10:00 SESSION 4: ENERGY AND POWER
Chair: Yuanyuan Zhou, University of Illinois

Software Assisted Issue Queue Power Reduction [PDF]
Timothy M. Jones, University of Edinburgh
Michael F. P. O'Boyle, University of Edinburgh
Jaume Abella, Universitat Politecnica de Catalunya
Antonio Gonzalez, Universitat Politecnica de Catalunya and Intel Labs
On the Limits of Leakage Power Reduction in Caches [PDF] [Slides]
Yan Meng, University of California, Santa Barbara
Timothy Sherwood, University of California, Santa Barbara
Ryan Kastner, University of California, Santa Barbara
Heat Stroke: Power-Density-Based Denial of Service in SMT [PDF] [Slides]
Jahangir Hasan, Purdue University
Ankit Jalote, Purdue University
T. N. Vijaykumar, Purdue University
Carla Brodley, Tufts University
Voltage and Frequency Control with Adaptive Reaction Time in Multiple-Clock-Domain Processors [PDF]
Qiang Wu, Princeton University
Philo Juang, Princeton University
Margaret Martonosi, Princeton University
Douglas W. Clark, Princeton University
10:00-10:30Break
10:30-12:30 SESSION 5: MEMORY SYSTEM ISSUES
Chair: John Carter, University of Utah

Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions [PDF]
Aamer Jaleel, University of Maryland, College Park
Bruce Jacob, University of Maryland, College Park
A Unified Compressed Memory Hierarchy [PDF]
Erik Hallnor, University of Michigan
Steven Reinhardt, University of Michigan
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors [PDF] [Slides]
Zhichun Zhu, University of Illinois at Chicago
Zhao Zhang, Iowa State University
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications [PDF] [Slides]
Lawrence Spracklen, Sun Microsystems
Yuan Chou, Sun Microsystems
Santosh G. Abraham, Sun Microsystems
12:30-1:30lunch (provided)
1:30-3:30 SESSION 6: INDUSTRIAL PERSPECTIVES (I)
Chair: Sanjay Patel, University of Illinois

Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors [PDF]
Hans Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel Tendler, IBM
The Soft Error Problem: An Architectural Perspective [PDF] [Slides] [Clarification on IBM's FIT Rate Targets for the Power 4 from Pia Sanda of IBM]
Shubu Mukherjee, Intel
Joel Emer, Intel
Steven Reinhardt, University of Michigan
Chip Multithreading: Opportunities and Challenges [PDF] [Slides]
Lawrence Spracklen, Sun Microsystems
Santosh G. Abraham, Sun Microsystems
Enterprise IT Trends and Implications for Architecture Research [PDF] [Slides]
Parthasarathy Ranganathan, HP Labs
Norman Jouppi, HP Labs
3:30-4:00Break
4:00-6:00 SESSION 7: INDUSTRIAL PERSPECTIVES (II)
Chair: Wen-Mei Hwu, University of Illinois

Power Efficient Processor Architecture and The Cell Processor [PDF] [Slides]
Peter Hofstee, IBM
Panel: "New Opportunities for Computer Architecture Research: An Industrial Perspective"
Organizer: Wen-Mei Hwu, University of Illinois[Slides]
Panelists:
Tim Chou, Oracle [Slides]
Peter Hofstee, IBM [Slides]
Emmett Kilgariff, NVIDIA [Slides]
Chuck Moore, AMD [Slides]
Justin Rattner, Intel [Slides]
7:00-10:00Evening Social Activity: Boat Tour of the San Francisco Bay


Wednesday February 16, 2004


8:00-9:00 SESSION 8: EVALUATION METHODOLOGIES
Chair: Pradip Bose, IBM

Characterizing and Comparing Prevailing Simulation Techniques [PDF]
Joshua J. Yi, Freescale Semiconductor
Sreekumar V. Kodakara, University of Minnesota
Resit Sendag, University of Rhode Island
David J. Lilja, University of Minnesota
Douglas M. Hawkins, University of Minnesota
Transition Phase Classification and Prediction [PDF]
Jeremy Lau, University of California, San Diego
Stefan Schoenmackers, University of California, San Diego
Brad Calder, University of California, San Diego
9:00-10:00 SESSION 9: SOFTWARE DEBUGGING SUPPORT
Chair: Yan Solihin, North Carolina State University

SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs [PDF]
Feng Qin, University of Illinois
Shan Lu, University of Illinios
Yuanyuan Zhou, University of Illinois
Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE [PDF] [Slides]
Marc L. Corliss, University of Pennsylvania
E. Christopher Lewis, University of Pennsylvania
Amir Roth, University of Pennsylvania
10:00-10:30Break
10:30-12:30 SESSION 10: MULTIPROCESSORS AND MULTITHREADING
Chair: Christos Kozyrakis, Stanford University

Unbounded Transactional Memory [PDF] [Slides]
C. Scott Ananian, MIT
Krste Asanovic, MIT
Bradley C. Kuszmaul, MIT
Charles E. Leiserson, MIT
Sean Lie, MIT
Improving Multiple-CMP Systems Using Token Coherence [PDF]
Michael R. Marty, University of Wisconsin, Madison
Jesse D. Bingham, University of British Columbia
Mark D. Hill, University of Wisconsin, Madison
Alan J. Hu, University of British Columbia
Milo M.K. Martin, University of Pennsylvania
David A. Wood, University of Wisconsin, Madison
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture [PDF] [Slides]
Dhruba Chandra, North Carolina State University
Fei Guo, North Carolina State University
Seongbeom Kim, North Carolina State University
Yan Solihin, North Carolina State University
SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors [PDF] [Slides]
Youtao Zhang, University of Texas at Dallas
Lan Gao, University of California, Riverside
Jun Yang, University of California, Riverside
Xiangyu Zhang, University of Arizona
Rajiv Gupta, University of Arizona