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HPCA-11 Final Program |
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Saturday February 12, 2005 |
| 8:30-5:00 All Day Events |
Tutorial T2: All You Want To Know About Circuits As An Architect But Were Afraid To Ask
Shih-Lien Lu, MRL/MTL IntelWorkshop W1: CAECW-8: Computer Architecture Evaluation using Commercial Workloads Kimberly Keeton, HP LabsWorkshop W2: HPCRI: High Performance Computing Reliability Issues Padma Apparao, Intel Labs |
| 1:00-5:00 Afternoon Events |
Tutorial T1: A Practical Approach To Performance Analysis And Modeling Of Large-Scale Systems
Adolfy Hoisie, Los Alamos National Laboratory |
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Sunday February 13, 2005 |
| 8:30-12:00 Morning Events |
Tutorial T3: Volatile Memory Performance Comparison
J. Thomas Pawlowski, Micron Technology, Inc. |
| 8:30-5:00 All Day Events |
Workshop W4: INTERACT-9: Interaction between Compilers and Computer Architectures
Gyungho Lee, University of Illinois at ChicagoWorkshop W5: PPHEC-2: Productivity and Performance in High-End Computing Ram Rajamony, IBMWorkshop W6: Hardware Performance Monitor Design and Functionality Olaf Lubeck, Los Alamos National Laboratory |
| 1:00-5:00 Afternoon Events |
Workshop W3: Architecture Research using FPGA Platforms
Arvind, MIT |
| 6:30-8:00 | Reception at the hotel |
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Monday February 14, 2005 |
| 8:15-8:30 | Welcome |
| 8:30-9:30 | Keynote Speech: Trends in High-Performance Processors Fred Weber, Chief Technology Officer, AMD Chair: Josep Torrellas |
| 9:30-10:00 | Break |
| 10:00-12:00 | SESSION 1: PROCESSOR ARCHITECTURE Chair: Antonio Gonzalez, Universitat Politecnica de Catalunya and Intel Labs Multithreaded Value Prediction [PDF] Nathan Tuck, University of California, San DiegoCheckpointed Early Load Retirement [PDF] Nevin Kιrman, Cornell UniversityMicroarchitectural Wire Management for Performance and Power in Partitioned Architectures [PDF] [Slides] Rajeev Balasubramonian, University of UtahA Small, Fast and Low-Power Register File by Bit-Partitioning [PDF] [Slides] Masaaki Kondo, University of Tokyo |
| 12:00-1:30 | Intel-sponsored lunch |
| 1:30-3:30 | SESSION 2: TEMPERATURE, ENERGY, AND POWER Chair: Krste Asanovic, MIT Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses [PDF] Krishnan Sundaresan, Michigan State UniversityDistributing the Frontend for Temperature Reduction [PDF] Pedro Chaparro Monferrer, Universitat Politecnica de Catalunya and Intel LabsPerformance, Energy, and Thermal Considerations for SMT and CMP Architectures [PDF] [Slides] Yingmin Li, University of VirginiaTapping ZettaRAM for Low-Power Memory Systems [PDF] [Slides] Ravi K. Venkatesan, North Carolina State University |
| 3:30-4:00 | Break |
| 4:00-6:00 | SESSION 3: COMMUNICATION ARCHITECTURES Chair: Timothy Pinkston, University of Southern California An Efficient Programmable 10 Gigabit Ethernet Network Interface Card [PDF] [Slides] Paul Willmann, Rice University Hyong-youb Kim, Rice University Scott Rixner, Rice University Vijay S. Pai, Purdue UniversityA New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks [PDF] [Slides] J. Duato, Universitat Politecnica de Valencia, Spain I. Johnson, Xyratex, United Kingdom J. Flich, Universitat Politecnica de Valencia, Spain F. Naven, Xyratex, United Kingdom P. García, Universidad de Castilla-La Mancha, Spain T. Nachiondo, Universitat Politecnica de Valencia, SpainExploring the Design Space of Power-Aware Opto-Electronic Networked Systems [PDF] Xuning Chen, Princeton University Yue-kai Huang, Princeton University Li-Shiuan Peh, Princeton University Paul Prucnal, Princeton University Gu-Yeon Wei, Harvard UniversityScatter-Add in Data Parallel Architectures [PDF] Jung Ho Ahn, Stanford University Mattan Erez, Stanford University Bill Dally, Stanford University |
| 6:30-8:00 | TCCA Business Meeting |
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Tuesday February 15, 2004 |
| 8:00-10:00 | SESSION 4: ENERGY AND POWER Chair: Yuanyuan Zhou, University of Illinois Software Assisted Issue Queue Power Reduction [PDF] Timothy M. Jones, University of EdinburghOn the Limits of Leakage Power Reduction in Caches [PDF] [Slides] Yan Meng, University of California, Santa BarbaraHeat Stroke: Power-Density-Based Denial of Service in SMT [PDF] [Slides] Jahangir Hasan, Purdue UniversityVoltage and Frequency Control with Adaptive Reaction Time in Multiple-Clock-Domain Processors [PDF] Qiang Wu, Princeton University |
| 10:00-10:30 | Break |
| 10:30-12:30 | SESSION 5: MEMORY SYSTEM ISSUES Chair: John Carter, University of Utah Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions [PDF] Aamer Jaleel, University of Maryland, College ParkA Unified Compressed Memory Hierarchy [PDF] Erik Hallnor, University of MichiganA Performance Comparison of DRAM Memory System Optimizations for SMT Processors [PDF] [Slides] Zhichun Zhu, University of Illinois at ChicagoEffective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications [PDF] [Slides] Lawrence Spracklen, Sun Microsystems |
| 12:30-1:30 | lunch (provided) |
| 1:30-3:30 | SESSION 6: INDUSTRIAL PERSPECTIVES (I) Chair: Sanjay Patel, University of Illinois Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors [PDF] Hans Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel Tendler, IBMThe Soft Error Problem: An Architectural Perspective [PDF] [Slides] [Clarification on IBM's FIT Rate Targets for the Power 4 from Pia Sanda of IBM] Shubu Mukherjee, IntelChip Multithreading: Opportunities and Challenges [PDF] [Slides] Lawrence Spracklen, Sun MicrosystemsEnterprise IT Trends and Implications for Architecture Research [PDF] [Slides] Parthasarathy Ranganathan, HP Labs |
| 3:30-4:00 | Break |
| 4:00-6:00 | SESSION 7: INDUSTRIAL PERSPECTIVES (II) Chair: Wen-Mei Hwu, University of Illinois Power Efficient Processor Architecture and The Cell Processor [PDF] [Slides] Peter Hofstee, IBMPanel: "New Opportunities for Computer Architecture Research: An Industrial Perspective" Organizer: Wen-Mei Hwu, University of Illinois[Slides] Panelists: |
| 7:00-10:00 | Evening Social Activity: Boat Tour of the San Francisco Bay |
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Wednesday February 16, 2004 |
| 8:00-9:00 | SESSION 8: EVALUATION METHODOLOGIES Chair: Pradip Bose, IBM Characterizing and Comparing Prevailing Simulation Techniques [PDF] Joshua J. Yi, Freescale SemiconductorTransition Phase Classification and Prediction [PDF] Jeremy Lau, University of California, San Diego |
9:00-10:00 | SESSION 9: SOFTWARE DEBUGGING SUPPORT Chair: Yan Solihin, North Carolina State University SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs [PDF] Feng Qin, University of IllinoisLow-Overhead Interactive Debugging via Dynamic Instrumentation with DISE [PDF] [Slides] Marc L. Corliss, University of Pennsylvania |
| 10:00-10:30 | Break |
| 10:30-12:30 | SESSION 10: MULTIPROCESSORS AND MULTITHREADING Chair: Christos Kozyrakis, Stanford University Unbounded Transactional Memory [PDF] [Slides] C. Scott Ananian, MITImproving Multiple-CMP Systems Using Token Coherence [PDF] Michael R. Marty, University of Wisconsin, MadisonPredicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture [PDF] [Slides] Dhruba Chandra, North Carolina State UniversitySENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors [PDF] [Slides] Youtao Zhang, University of Texas at Dallas |