Tutorial: Volatile Memory Performance Comparison

 
To be held at
the 11th International Symposium on High-Performance Computer Architecture (HPCA-11)
Palace Hotel, San Francisco
Sunday Morning, February 13th, 2005

Presenter: J. Thomas Pawlowski, Micron Technology, Inc.


Abstract:

Between vendor vested interests, presentation hype and datasheet specsmanship, it is often difficult to determine which memory devices are truly the most appropriate for an application in question. This is true for all volatile memory devices. This tutorial will objectively examine the memories available today and in the reasonably near future, including SRAMs such as QDR II, DDR II and QDR III; DRAMs such as DDR2, GDDR3, FCRAM, RLDRAM and XDR. A brief description will be made concerning external operation of the major devices and where necessary some description of internal operation. The devices will be compared by performance (usable bandwidth under various operating scenarios, fairly accounting for signal count). Example operating scenarios include random operations, streaming requests with defined read/write ratios and resource predictability, streaming requests with defined read/write ratios but no predictable resource availability, etc. Performance comparisons are made using a cycle-accurate memory comparison software tool written by the author and empirically verified. Conclusions will be drawn for each major operating scenario concerning performance with some discussion of relative memory implementation cost. Wherever possible, practical application examples will be illustrated to make the operating scenarios relevant to the system design tasks faced today and in the reasonably near future.


Presenter Biography:

As Senior Director of Architecture Development in Micron’s NetCom Group, J. Thomas Pawlowski is responsible for Micron memory product definition for networking and communications applications including products built on DRAM and FLASH processes. During his tenure at Micron, Thomas has created or co-created the following DRAM and SRAM devices: reduced latency DRAM II (RLDRAM™ II); pipelined, burst, synchronous SRAM (used in Pentium® and PowerPC® systems); Zero Bus Turnaround™ (ZBT®) SRAM (used in network and communication systems); double data rate (DDR) SRAM; and Quad Data Rate™ (QDR™) SRAM (versions I, II, and III). Thomas holds over 70 U.S. and international patents with more pending.

Prior to joining Micron in 1992, Thomas spent eight years at Allied Signal Aerospace. He holds a bachelor of applied science degree in electrical engineering from the University of Waterloo, Ontario, Canada.