HPCA-12 Final Program
Saturday Feb. 11th 2006
08:00am-08:30am	Breakfast
08:30am-05:00pm All Day Events*	Tutorial T2: The Design and Implementation of the TRIPS EDGE Architecture Doug Burger (Univ of Texas at Austin), Steve Keckler (Univ of Texas at Austin), Kathryn McKinley (Univ of Texas at Austin)
	Workshop W1: HPCRI-2: Workshop on High Performance Computing Reliability Issues Padma Apparao (Intel Labs), Greg Averill (Digital Enterprise Group)
	Workshop W2: WMPI-2006: Workshop on Memory Performance Issues John Carter (University of Utah), Lixin Zhang (IBM Austin Research Lab)
01:00pm-05:00pm Afternoon Events*	Tutorial T1: Microprocessor Memory Array Circuits for Architects Shih-Lien Lu (Microarchitecture Research, Intel Labs), Nam Sung Kim (Circuit Research, Intel Labs), Steven Hsu (Circuit Research, Intel Labs)
Sunday Feb. 12th 2006
08:00am-08:30am	Breakfast
08:30am-05:00pm All Day Events*	Workshop W4: CAECW-9: Workshop on Computer Architecture Evaluation using Commercial Workloads Lieven Eeckhout (Ghent University), Ravi Iyer (Intel Labs)
	Workshop W5: INTERACT-10: Workshop on Interaction between Compilers and Computer Architectures Sangyeun Cho (Univ. of Pittsburgh), Gyungho Lee (Univ. of Illinois at Chicago)
	Workshop W6: PPHEC-3: Workshop on Productivity and Performance in High-End Computing Ram Rajamony (IBM, Program Chair), Nick Nystrom (PSC), Philip Johnson (Univ. of Hawaii), Vijay Saraswat (IBM), Larry Votta (Sun)
	Workshop W7: WARFP-2006: Workshop on Architecture Research using FPGA Platforms Arvind (MIT), Krste Asanovic (MIT), Derek Chiou (UT Austin), James Hoe (CMU), Christoforos Kozyrakis (Stanford), Shih-Lien Lu (Intel)
	Workshop W8: RIDMS-1: Workshop on Real Time, Interactive, and Digital Media Supercomputing Ashwini K. Nanda (IBM TJ Watson Research Center)
01:00pm-05:00pm Afternoon Events*	Workshop W3: WISA-2006: Workshop on IntroSpective Architectures Hsien-Hsin S. Lee (Georgia Tech), Trevor Mudge (Michigan), Milos Prvulovic (Georgia Tech)
06:00pm-08:00pm	HPCA Reception at hotel
* All workshops and tutorials above will take place simultaneously with following breaks. 10:00am-10:30am: break, 12:00pm-01:00pm: lunch (provided), 03:00pm-03:30pm: break
Monday Feb. 13th 2006
08:00am-08:30am	Breakfast
08:30am-08:45am	Welcome: Craig Chase, Yale Patt and Chita R. Das
08:45am-09:45am	Keynote I: New Architectures for a New Biology [Slides] David E. Shaw, D.E. Shaw & Co.
09:45am-10:15am	Break
10:15am-11:45am	SESSION 1: Chip Multiprocessors (CMPs)
	Chair: Josep Torrellas (UIUC)
	BulletProof: A Defect-Tolerant CMP Switch Architecture [PDF] Kypros Constantinides (University of Michigan), Stephen Plaza (University of Michigan), Jason Blome (University of Michigan), Bin Zhang (University of Texas), Valeria Bertacco (University of Michigan), Scott Mahlke (University of Michigan), Todd Austin (University of Michigan), Michael Orshansky (University of Texas)
	CMP Design Space Exploration Subject to Physical Constraints [PDF] Yingmin Li (University of Virginia), Benjamin Lee (Harvard University), David Brooks (Harvard University), Zhigang Hu (IBM T.J.Watson), Kevin Skadron (University of Virginia)
	Exploiting Parallelism and Structure to Accelerate the Simulation of Chip Multi-processors [PDF] David A. Penry (Princeton University), Daniel Fay (University of Colorado at Boulder), David Hodgdon (University of Colorado at Boulder), Ryan Wells (Princeton University), Graham Schelle (University of Colorado at Boulder), David I. August (Princeton University), Dan Connors (University of Colorado at Boulder)
11:45am-01:15pm	Lunch (provided)
01:15pm-02:45pm	SESSION 2: Processor Architecture
	Chair: James C. Hoe (CMU)
	An Approach for Implementing Efficient Superscalar CISC Processors [PDF] Shiliang Hu (Univ. of Wisconsin – Madison), Ilhyun Kim (Intel), Mikko H. Lipasti (Univ. of Wisconsin – Madison), James E. Smith (Univ. of Wisconsin – Madison)
	A Decoupled KILO-Instruction Processor [PDF] Miquel Pericàs (Universitat Politecnica de Catalunya (UPC) & Barcelona Supercomputing Center (BSC)), Adrian Cristal (UPC & BSC), Ruben González (UPC), Daniel A. Jiménez (Rutgers University), Mateo Valero (UPC & BSC)
	Store Vectors for Scalable Memory Dependence Prediction and Scheduling [PDF] Samantika Subramaniam (Georgia Tech), Gabriel H. Loh (Georgia Tech)
02:45pm-03:15pm	Break
03:15pm-04:45pm	SESSION 3: Parallel Architecture
	Chair: Ashwini Nanda (IBM T.J. Watson)
	Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors [PDF] Jian Li (Cornell University), José F. Martínez (Cornell University)
	Last Level Cache (LLC) Performance of Data Mining Workloads On a CMP — A Case Study of Parallel Bioinformatics Workloads [PDF] Aamer Jaleel (Intel Corporation), Matthew Mattina (Tilera Corporation), Bruce Jacob (University of Maryland, College Park)
	Construction and Use of Linear Regression Models for Processor Performance Analysis [PDF] P. J. Joseph (Indian Institute of Science), Kapil Vaswani (Indian Institute of Science), Matthew J. Thazhuthaveetil (Indian Institute of Science)
04:45pm-05:00pm	Break
05:00pm-06:30pm	Panel: Patenting the Fruits of Academic Research: What are the Implications? Moderator: Rich Belgard Panel members: John Amster, Intellectual Ventures, Bellevue, WA Rich Belgard, Consultant, Saratoga, CA Mike Heim, Heim, Payne & Chorush, LLP, Houston, TX Trevor Mudge, University of Mighigan, Ann Arbor, MI Yale Patt, University of Texas, Austin, TX
07:00pm-08:00pm	TCCA Business Meeting
Tuesday Feb. 14th 2006
08:00am-08:45am	Breakfast
08:45am-09:45am	Keynote II: Chip-multiprocessing and Beyond [Slides] Per Stenström, Chalmers University of Technology
09:45am-10:15am	Break
10:15am-11:45am	SESSION 4: Energy and Power
	Chair: Trevor Mudge (Michigan)
	Probabilistic Counter Updates for Predictor Hysteresis and Stratification [PDF] Nicholas Riley (UIUC), Craig Zilles (UIUC)
	Phase Characterization for Power: Evaluating Control-Flow-Based and Event-Counter-Based Techniques [PDF] Canturk Isci (Princeton University), Margaret Martonosi (Princeton University)
	DMA-Aware Memory Energy Management [PDF] Vivek Pandey (UIUC), Weihang Jiang (UIUC), Yuanyuan Zhou (UIUC), Ricardo Bianchini (Rutgers University)
11:45am-01:15pm	Lunch (provided)
01:15pm-02:45pm	SESSION 5: Memory Systems
	Chair: Qing Yang (University of Rhode Island)
	Increasing the Cache Efficiency by Eliminating Noise [PDF] Prateek Pujara (Binghamton University), Aneesh Aggarwal (Binghamton University)
	Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM [PDF] Ravi K. Venkatesan (North Carolina State University), Stephen Herr (North Carolina State University), Eric Rotenberg (North Carolina State University)
	Completely Verifying Memory Consistency of Test Program Executions [PDF] Chaiyasit Manovit (Sun Microsystems, Sunnyvale, CA), Sudheendra Hangal (Magic Lamp Software, Bangalore, India)
02:45pm-03:15pm	Break
03:15pm-04:15pm	SESSION 6: Disk and High Performance I/O
	Chair: Ricardo Bianchini (Rutgers Univ.)
	Understanding the Performance-Temperature Interactions in Disk I/O of Server Workloads [PDF] Youngjae Kim (Pennsylvania State University), Sudhanva Gurumurthi (University of Virginia), Anand Sivasubramaniam (Pennsylvania State University)
	High Performance File I/O for The Blue Gene/L Supercomputer [PDF] H. Yu (IBM TJ Watson Research Centre), R. K. Sahoo (IBM TJ Watson Research Centre), C. Howson (IBM TJ Watson Research Centre), G. Almási (IBM TJ Watson Research Centre), J. G. Castaños (IBM TJ Watson Research Centre), M. Gupta (IBM TJ Watson Research Centre), J. E. Moreira (IBM System & Technology Group), J. J. Parker (IBM System & Technology Group), T. E. Engelsiepen (IBM Almaden Research Center), R. B. Ross (Argonne National Lab), R. Thakur (Argonne National Lab), R. Latham (Argonne National Lab), W. D. Gropp (Argonne National Lab)
04:15pm-04:30pm	Break
04:30pm-06:00pm	SESSION 7: Industrial Perspectives on Challenges for Next-Generation Computer Systems (Invited presentation)
	Chair: Mazin Yousif (Intel)
	Platform Design Challenges with Many cores [Slides] Raj Yavatkar (Intel Fellow)
	System IO Network Evolution - Closing Requirement Gaps [Slides] Renato Recio (IBM Distinguished Engineer)
	The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth [Slides] Philip Emma (Manager, IBM)
06:30pm-10:30pm	Conference Banquet
Wednesday Feb. 15th 2006
08:00am-09:30am	SESSION 8: Fault-Tolerant Architecture and Security
	Chair: Vijaykrishnan Narayanan (Penn State Univ.)
	ReViveI/O: Efficient Handling of I/O in Highly-Available Rollback-Recovery Servers [PDF] Jun Nakano (UIUC), Pablo Montesinos (UIUC), Kourosh Gharachorloo (Google), Josep Torrellas (UIUC),
	Reducing Resource Redundancy for Concurrent Error Detection Techniques in High Performance Microprocessors [PDF] Sumeet Kumar (Binghamton University), Aneesh Aggarwal (Binghamton University)
	InfoShield: A Security Architecture for Protecting Information Usage in Memory [PDF] Weidong Shi (Georgia Tech), Joshua B. Fryman (Intel), Guofei Gu (Georgia Tech), Hsien-Hsin S. Lee (Georgia Tech), Youtao Zhang (University of Pittsburgh), Jun Yang (University of California, Riverside)
09:30am-09:45am	Break
09:45am-11:15am	SESSION 9: Hardware/Software Tradeoffs
	Chair: Doug Burger (UT Austin)
	CORD: Cost-effective (and nearly overhead-free) Order-Recording and Data race detection [PDF] Milos Prvulovic (Georgia Tech)
	Software-Hardware Cooperative Memory Disambiguation [PDF] Ruke Huang (Univ. of Rochester), Alok Garg (Univ. of Rochester), Michael Huang (Univ. of Rochester)
	LogTM: Log-based Transactional Memory [PDF] Kevin E. Moore (University of Wisconsin-Madison), Jayaram Bobba (University of Wisconsin-Madison), Michelle J. Moravan (University of Wisconsin-Madison), Mark D. Hill (University of Wisconsin-Madison), David A. Wood (University of Wisconsin-Madison)
11:15am-11:30am	Break
11:30am-01:00pm	SESSION 10: Multi-Threaded Systems
	Chair: Milos Prvulovic (GATECH)
	The Common Case Transactional Behavior of Multithreaded Programs [PDF] JaeWoong Chung (Stanford University), Hassan Chafi (Stanford University), Chi Cao Minh (Stanford University), Austen McDonald (Stanford University), Brian Carlstrom (Stanford University), Christos Kozyrakis (Stanford University), Kunle Olukotun (Stanford University)
	Speculative Synchronization and Thread Management for Fine Granularity Threads [PDF] Alex Gontmakher (Technion), Avi Mendelson (Intel), Assaf Schuster (Technion), Gregory Shklover (Technion)
	Efficient Instruction Schedulers for SMT Processors [PDF] Joseph Sharkey (SUNY Binghamton), Dmitry Ponomarev (SUNY Binghamton)