Tutorial on Microprocessor Memory Array Circuits for Architects

Presenters:
Shih-Lien Lu, Microarchitecture Research, Intel Labs
Nam Sung Kim, Circuit Research, Intel Labs
Steven Hsu, Circuit Research, Intel Labs

Abstract:

More and more devices on a microprocessor are devoted to memory arrays nowadays. For example, more than 1/2 of the devices among the 3 millions plus transistors on the first generation pPentiumTM are used for implementing cache, table, register files, etc. However, these memory arrays are quite different in circuit and have different charcteristics due to their requirement. Some are based on small signals and others are single ended. This tutorial intends to extract out general technology and circuit information for microarchitects and architects different types of memory array circuits used ina modern microprocessor. The intention is to provide a general understanding of the circuit so correct tradeoffs can be made. 

A list of topics to be covered and some of their related bibliography:

• SRAM arrays and organization - decoder, word-line, local and global bit-line, column muxes, sub-array
• Size, performance, Vcc_min, and yield tradeoffs of SRAM arrays
• SRAM circuit-level leakage reduction techniques
• Pitfalls in existing cache performance / power estimation tools
• Register files - multiple read/write ports, power reduction, leakage control
• Special arrays - content addressable memory
• Future treands challenges of memory arrays on microprocessors