Tutorial on the Design and Implementation of the TRIPS EDGE Architecture

Tutorial on Microprocessor Memory Array Circuits for Architects

Presenters:
Doug Burger
Steve Keckler
Robert McDonald
Ramdas Nagarajan
Nitya Ranganathan
Haiming Liu
Karu Sankaralingam
Premkishore Shivakumar
Simha Sethumadhavan
Changkyyu Kim
Paul Gratz
Kathryn McKinley
Aaron Smith

Abstract:

This tutorial will cover the design and implementation of an EDGE
(Explicit Data Graph Execution) architecture, using the TRIPS
architecture and prototype as an illustrative example. We will delve
into the TRIPS architecture and microarchitecture, covering the
portions of the design that differ substantively from conventional
RISC or CISC processors. In addition to covering the ISA and the
microarchitecture in depth, we will describe the additions and
structural changes required for a conventional compiler to target an
EDGE architecture with heavy optimization.

Duration: Full day