Austin, February 11th and 12th, 2006
Tutorial:
T1:
Microprocessor
Memory Array Circuits for Architects
Shih-Lien
Lu, Microarchitecture Research, Intel Labs
Nam
Sung Kim, Circuit Research, Intel Labs
Steven
Hsu, Circuit Research, Intel Labs
T2: The
Design
and Implementation of the TRIPS EDGE Architecture
Doug Burger, Univ of Texas at Austin
Steve
Keckler, Univ of Texas at Austin
Kathryn
McKinley, Univ of Texas at Austin
and others....
Workshops:
W1:
Workshop on High
Performance Computing Reliability Issues (HPCRI-2)
W2:
Workshop
on Memory Performance Issues (WMPI)
W3:
Workshop
on IntroSpective Architectures
(WISA)
W4:
Workshop on Computer Architecture
Evaluation using Commercial Workloads (CAECW-9)
W5: Workshop on Interaction between
Compilers
and Computer Architectures
(INTERACT-10)
W6: Workshop on
Productivity and
Performance in High-End Computing (PPHEC-3)
W7: Workshop on
Architecture Research
using FPGA Platforms (WARFP)
W8:
Workshop on Real Time,
Interactive,
and Digital Media Supercomputing (RIDMS-1)
Schedule
| Saturday
February 11th |
| Morning |
Afternoon |
-
|
T1:
Memory Circuit Tutorial |
T2: TRIPS
|
W1:
HPCRI
|
W2:
WMPI
|
| Sunday February
12th |
| Morning |
Afternoon |
-
|
W3: WISA
|
W4: CAECW
|
W5: INTERACT
|
W6: PPHEC
|
| W7: WARFP |
| W8: RIDMS |
|
|