8:20-8:40	Opening Remarks
8:40-10:00	Power-Aware Architecture/Microarchitecture Early-Stage Definition of LPX: A Low Power Issue-Execute Processor Prototype P. Bose, D. Brooks, A. Buyuktosunoglu, P. Cook, K. Das, P. Emma, M. Gschwind, H. Jacobson, T. Karkhanis, S. Schuster, J. E. Smith, V. Srinivasan, V. Zyuban, D. Albonesi, S. Dwarkadas IBM T. J. Watson/U. Rochester/U. Wisconsin Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints K. Inoue, V. Moshnyaga, K. Murakami Fukuoka U./Kyushu U. A Hardware Architecture for Dynamic Performance and Energy Adaptation P. Stanley-Marbell, M. S. Hsiao, U. Kremer CMU/Virginia Tech/Rutgers U. Multi-Processor Computer System Having Low Power Consumption C. M. Olsen, L. A. Morrow IBM Research
10:00-10:30	Break
10:30-11:30	Keynote Address  Power: The Next Frontier Ronny Ronen Intel Labs (MRL, Israel)
11:30-1:00	Lunch
1:00-2:00	Power-Aware Real-Time Systems An Integrated Heuristic Approach to Power-Aware Real-Time Scheduling P. Mejia-Alvarez, E. Levner, D. Mosse CINVESTAV-IPN/Holon Tech/U. Pittsburgh Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources J. Liu, P. H. Chou, N. Bagherzadeh U. Irvine A Low-Power Content-Adaptive Texture Mapping Architecture for Real-Time 3D Graphics J. Euh, J. Chittamuru, W. Burlesson U. Massachusetts
2:00-3:00	Power Modeling and Monitoring Energy-Driven Statistical Profiling Detecting Software Hotspots F. Chang, K. Farkas, P. Ranganathan Compaq WRL Modeling of DRAM Power Control Policies Using Deterministic and Stochastic Petri Nets X. Fan, C. Ellis, A. R. Lebeck Duke U. SimDVS: An Integrated Simulation Environment for Performance Evaluation of Dynamic Voltage Scaling Algorithms D. Shin, W. Kim, J. Jeon, J. Kim Seoul National U.
3:00-3:30	Break
3:30-4:30	Power-Aware OS & Compilers Application-Supported Device Management for Energy and Performance T. Heath, E. Pinheiro, R. Bianchini Rutgers U. Energy-Efficient Server Clusters E. N. Elnozahy, M. Kistler, R. Rajamony IBM Research Single Region vs. Multiple Regions: A Comparison of Different Compiler-Directed Dynamic Voltage Scheduling Approaches C.-H. Hsu, U. Kremer Rutgers U.
4:30-5:00	Discussion/Closing Remarks